Hardware-accelerated event-graph neural networks for low-latency time-series classification on SoC FPGA

This repository is intended to reproduce and run experiments for a FPGA implementation of event-based audio data processing system for spoken word classification.
The system employs an event-by-event processing approach using graph neural networks. The weights provided in the project enable processing of spoken digits and were obtained through training on the Spiking Heidelberg Digits Dataset (SHD).

The repository includes all necessary hardware modules (SystemVerilog RTL files), along with the required IP cores and memory initialization files.

The data and implementation are associated with the following publication:

Hardware-accelerated event-graph neural networks for low-latency time-series classification on SoC FPGA
Hiroshi Nakano, Krzysztof Błachut, Kamil Jeziorek, Piotr Wzorek, Manon Dampfhoffer, Thomas Mesquida, Hiroaki Nishi, Tomasz Kryjak, Thomas Dalgaty.

In: Applied Reconfigurable Computing: Architectures, Tools, and Applications – ARC 2025 Proceedings,
21st International Symposium, ARC 2025 – Applied Reconfigurable Computing,
Seville, Spain, April 9–11, 2025.
Published by Springer in the Lecture Notes in Computer Science (LNCS 15594), pp. 51–68.
ISBN: 978-3-031-87994-4, eISBN: 978-3-031-87995-1.

This work was supported by the Polish National Science Centre project 2024/53/N/ST6/04331.