Verolig-A Code for Josephson Field-Effect Transistor Modeling.

The Verilog-A implementation corresponding to the gate-dependent compact model of the $L_g = 350$~nm device discussed in Sec.~III of the journal article Device Models for Josephson Field-Effect Transistors and for Superconducting Integrated Circuits. This article was submitted to the IEEE Journal of the Electron Devices Society and is still under review. 

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// Graphene Josephson FET (JoFET) Verilog-A Model
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// Description:
// Compact Verilog-A model of a graphene-based Josephson field-effect transistor
// (JoFET) based on an RCSJ formulation with gate-tunable resistance and
// critical current.
//
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// Usage in ADS:
//
// - This model is intended to be used in Keysight ADS.
// - Create a symbol from this Verilog-A module.
// - Ensure the symbol is properly linked to this .va file.
// - The symbol should expose three terminals: d (drain), s (source), g (gate).
//
// Recommended simulation setup:
//   * Gate (g): connect to a voltage source (Vg bias)
//   * Drain–Source (d–s): connect to a current source for current sweep
//   * Use transient simulation to observe device behavior
//
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// Notes:
//
// - Designed primarily for transient simulations.
// - Phase dynamics implemented using time integration (idt).
//
// - Optional small conductance is included across d–s for numerical convergence:
//     I(d, s) <+ gmin * V(d, s)
//   This helps avoid convergence issues in ADS. It can be reduced or removed
//   if not required, depending on simulation stability.
//
// - If discipline/nature definitions are already provided by the simulator
//   environment (e.g., via "disciplines.vams"), any duplicate header
//  Declarations should be removed to avoid redefinition errors.
//  Parameter Notes:
//   mu        : carrier mobility (m^2/Vs)
//   nr        : residual carrier density (m^-2)
//   Rc        : contact resistance (Ohm)
//   alpha     : scaling factor for Ic
//   Delta_ind : induced superconducting gap (J)
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