Published March 16, 2026 | Version v1 (OOPSLA26-R2-AEC-Final)

When FPGA Meets Dataflow Analysis: An Explorative Step (Artifact)

  • 1. ROR icon Nanjing University
  • 2. ROR icon Aarhus University

Description

This artifact accompanies our paper, When FPGA Meets Dataflow Analysis: An Explorative Step.
Because reproducing the FPGA-accelerated experiments requires access to the FPGA platform used in the paper, which is typically unavailable to readers, we provide materials to support reproduction to the extent possible:

  • The full open-source implementation of our proposed FpgaFlow, including the FPGA hardware design (fpga_code.zip) and host-side software (tai-e_code.zip);
  • Deployment and experiment-reproduction guidance (README.pdf);
  • Screen recordings of experiments conducted on our machine (videos.zip) and documentation explaining the video outputs and relating them to the corresponding results reported in the paper (videos.md).

Files

README.pdf

Files (13.4 GB)

Name Size
md5:861772e828862a4c221e05a00f697e70
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md5:18b7c4856c0b11b450375feeefbc1777
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md5:a174498438b6fa8da72f0c8d39c6b7ad
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md5:8729f0a888e8540ceb4acb6d221a7b5e
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