MINISA: Minimal Instruction Set Architecture for Next-gen Reconfigurable Inference Accelerato

This artifact contains the MINISA ISA toolchain for the FEATHER+ reconfigurable accelerator.
It includes: (1) the MINISA compiler that lowers GEMM workloads to variable-width ISA instructions, (2) a cycle-accurate analytical performance model with a 5-engine asynchronous execution simulator, (3) a GUI to illustrate how FEATHER+ works with cycle-by-cycle animation
(4) instruction compression analysis comparing MINISA against explicit micro-configuration, and (5) latency comparison against GPU (NVIDIA RTX~5090) and TPU (Google TPU~v6e-8) baselines. The artifact reproduces all evaluation figures: instruction reduction ratios, speedup over micro-instruction, latency breakdown with compute utilization, and FEATHER+ vs. GPU/TPU latency comparison.