5500FP: A 24-Trit Balanced Ternary RISC Processor

We present the 5500FP, a 24-trit balanced ternary RISC processor implemented on FPGA, with a 120-instruction ISA, native atomic synchronization primitives, and an open hardware development board. The design demonstrates the practical feasibility of balanced ternary computing on modern reconfigurable hardware, providing a concrete platform for research into non-binary architectures without the barrier of custom silicon development.