Design and Reliability Analysis of a Pipeline RISC-V Processor Core

Reliability and performance are key design concerns for embedded processors deployed in space and safety-critical environments. This work enhances our previously developed Hardened RISC-V System-on-Chip (HARV-SoC) by implementing a pipelined architecture. This implementation improves execution efficiency while keeping the design straightforward to avoid reliability issues. Although the pipeline enhances performance, it entails trade-offs between performance and reliability depending on the chosen design options. We present a detailed analysis by performing a fault-injection simulation in the processor core that models the effects of Single-Event Upsets (SEUs) in the core's flip-flop elements, and by estimating the effects in future irradiation experiments. The results provide valuable insights into the processor's robustness and identify the critical elements for future hardening implementations targeting specific architectural components.