HARDWARE-EFFICIENT SYSTOLIC ARCHITECTURE FOR AES MIX COLUMN COMPUTATION

This paper presents a systolic array-based architec- tural framework for implementing the Mix Column and Inverse Mix Column layers of the AES (Rijndael) block cipher algorithm. Each processing element (PE) in the proposed systolic array performs Galois Field arithmetic operations to achieve diffusion through multiplications and additions. The systolic approach enables high-throughput and hardware-efficient computation compared to conventional AES implementations.Performance analysis based on the Figure of Merit (FOM) demonstrates notable improvements in throughput and resource utilization. AES remains one of the most secure and widely used cryp-tographic standards, providing strong diffusion and confusion characteristics. With the rapid growth of data-centric applica-tions and hardware security accelerators, the proposed systolic design contributes toward higher efficiency and scalability in cryptographic hardware implementations. The work includes details on layer partitioning, existing Mix Column methodologies, the proposed systolic PE design, FPGA synthesis outcomes, and comparative evaluation.