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Published December 23, 2025 | Version v1
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Mortise and Tenon Full Stack 1_ An Innovative Concept of Multi-Chip Integration Based on Mechanical Properties of Mortise and Tenon in the Post-Moore Era - Framework Construction and Adaptation Optimization

Authors/Creators

  • 1. Independent Researcher

Description

Abstract

As a forward-looking theoretical hypothesis, this study addresses the three core pain points of chips in the post-Moore era: the physical limit of two-dimensional integration, power consumption wall, and low interconnection efficiency, as well as the difficulty in meeting the differentiated needs of CPU, GPU, and AI chips through a single architecture. Breaking away from the inertial thinking of the semiconductor industry, it proposes an innovative concept of multi-chip integration inspired by the mechanical properties of mortise and tenon in traditional Chinese architecture (such as brackets in the Forbidden City and components of the Yingxian Wooden Pagoda). The core is to migrate the wisdom of "modular interlocking and force-thermal synergistic conduction" in traditional Chinese architecture to the micro-design of 1-10μm chips, constructing a four-dimensional collaborative architecture of "3D interlocking - multi-element synergy - function integration - scenario adaptation". By designing diversified mortise and tenon interconnection structures, three-layer three-dimensional computing units, function-oriented multi-material systems (compatible with silicon-based and non-silicon materials), vascularized heat dissipation networks, and standardized reconfigurable modules, customized adaptation of multi-chips is achieved. Based on the theoretical deduction of geometric topology and heat transfer, and cross-validation with 32 authoritative literatures, the number of interconnection nodes in this architecture is doubled compared with traditional 3D integration (interconnection freedom expanded from 3 directions to 6 directions). The theoretical computing power density of CPU/GPU/AI chips reaches 3 times, 4 times, and 3.5 times that of 28nm planar chips respectively, and the R&D cycle can be shortened by 40%[2]. This study provides a "non-technical breakthrough" interdisciplinary solution path for the multi-chip adaptation problem in the post-Moore era. Its ideas can be extended to multiple scenarios such as three-dimensional optoelectronics and flexible electronics, and core parameters need to be calibrated through subsequent experiments (not theoretical logical flaws). This study is a homologous innovation with the patent "A Reconfigurable Multi-Morphology Integration Architecture Inspired by Mortise and Tenon Mechanical Properties and Adaptive Compatibility Transfer Method" (China National Patent Application No.: 2025118556570; Application Date: 2025.12.10; PCT application is planned to be filed within 12 months), with highly consistent core theoretical logic.

 

Update 1: This is Not Merely a Hypothesis, but the Future (Beijing Time 15:22, March 4, 2026)

I once thought this paper, along with my work on brain-computer interfaces, would gain little traction for being too cutting-edge and groundbreaking—mere hypotheses in the eyes of many. However, as Zenodo finalized the download statistics over the past two days, I noticed this paper’s download figures are far from single-digit: with 21 views and 47 downloads, the download count is more than double the view count. This makes me realize that this research is highly valued and appreciated by scholars in academia and the semiconductor industry alike.
 
I need to state here that this paper is the first one I have ever written. It marks the beginning of my journey as an independent researcher, and also the starting point for my explorations into dynamic systems, game theory, communication theory, video studies, cosmology, and potentially more fields in the future. The discipline of Trait Lock Theory was derived from my third paper on dynamic systems, so starting from my fourth paper, I have essentially mastered the key to conducting research in any field. You can already perceive the embryonic form of this thinking in this paper: the reverse migration of the mechanical structure of mortise and tenon joints to the microcosmic field of semiconductors itself embodies the core idea of my Trait Lock Theory—penetrating the superficial manifestations to reach the essence. Though this discipline had not yet been formally established when I wrote this paper, its ideological prototype is still palpable.
 
With this understanding, I wish to be forthright: from the title of this paper, can you sense that it is the first installment of the Mortise and Tenon Full Stack series? In fact, I have already completed the second (Performance Volume) and third (Instruction Set-level Volume) installments. Taking traditional 28nm chips as the benchmark, the theoretical performance of my mortise and tenon structured chips can achieve a 192x performance boost. Why is this figure so staggering? Because my chip, with its 3D stereoscopic structure, achieves an intrinsic performance improvement through multiplication, in stark contrast to the additive performance gains of planar chips. Fundamentally, my chip adopts 16-bit as the benchmark number system—this alone delivers a 4x performance improvement over the traditional binary system, not to mention enhancements in other aspects. Moreover, this performance gain only refers to improvements at the physical or hardware level, with software-based boosts such as turbo boost not yet factored in. Thus, the 192x performance improvement can be understood as a side-effect-free native performance enhancement.
 
To put it in perspective in terms of equivalent quantity, my 28nm mortise and tenon structured chip is equivalent to 41.8 current 3nm process chips. This is the disruptive nature of my mortise and tenon architecture: it does not merely optimize existing manufacturing processes, but completely restructures the underlying logic of performance generation. Traditional chips have reached the end of the road in planar manufacturing, and my mortise and tenon chip has already outperformed all current chips even in its theoretical form. Even accounting for various losses in manufacturing and production, a practical performance boost of at least 150-160x can still be guaranteed upon commercialization. And what if more advanced processes such as 14nm, 7nm, 5nm, or 3nm are adopted?
 
Therefore, my statement that the mortise and tenon chip is the unrivaled optimal path for future 3D structured chips is no exaggeration, but a plain fact. The mature application and engineering validation of the mortise and tenon structure in ancient Chinese architecture span more than 3,000 years; its mechanical logic has stood the test of thousands of years of practice, proving to be stable and reliable, and there is practically no structural design that can surpass it. As for why the second installment has not been published: I intend to release it only after research teams or corporate research institutes collaborate with me to create a feasible prototype chip. It is necessary to develop the first viable chip based on the 28nm process before publishing the second paper—otherwise, the publication would be meaningless. Here, I simply aim to demonstrate the immense performance potential of my chip. Once the 28nm prototype chip is completed, we can proceed to tackle more advanced manufacturing processes such as 14nm, 7nm and 5nm. It is also worth noting that the success of a 28nm prototype would render all current traditional chips—including those produced by Intel, AMD, ARM, and Apple’s M1 series—no match for my mortise and tenon chip.
 
If you, or any interested enterprises and research institutes, aspire to shape the future, my mortise and tenon chip is an exceptional direction to pursue. At the very least, it represents a new architecture with a foreseeable and quantifiable theoretical performance— a rising sun and a beacon of hope, in contrast to the stagnant traditional chip industry that has hit its technological ceiling. Investing in the entirely new field of mortise and tenon chips is far more valuable than pouring resources into the traditional chip industry, where only marginal performance improvements are possible. This is the optimal and future-oriented path forward. The second installment (Performance Volume) will only be published upon the completion of the prototype chip, and its release will bring a qualitative surge in the stock price or valuation of the team or enterprise that develops the prototype.
 
I am a pragmatic researcher who values real-world implementation, and every paper I publish is a high-value academic achievement. Even if my foundational theories do not receive immediate attention due to their profundity, time will prove their worth. Furthermore, I will also write applied research papers to popularize these theories. If you are interested in mortise and tenon chips, I welcome your contact—my email address has always been publicly available. Even if no one reaches out, it is of little consequence to me: the semiconductor field is just a small part of my research scope, while for those working in it, it is the future. I am an originator of 0-to-1 theoretical frameworks, and my research is driven by curiosity. There are numerous more intriguing fields awaiting my exploration.
 
Ultimately, the commercialization of the mortise and tenon chip does not depend on me, but on you—enterprises, research institutes, and teams with the vision and resolve to innovate.

Abstract (Mandarin Chinese)

摘要

作为前瞻性理论假说,本研究针对后摩尔时代芯片 “二维集成物理极限、功耗墙、互连效率低” 三大核心痛点,及 CPU、GPU、AI 芯片差异化需求难以通过单一架构满足的难题,跳出半导体行业惯性思维,提出基于中国古建筑榫卯(如故宫斗拱、应县木塔构件)力学特性启发的多芯片集成创新构想。核心是将中国古建筑 “模块化互锁、力 - 热协同传导” 智慧迁移至 1-10μm 芯片微观设计,构建 “三维互锁 - 多元协同 - 功能融合 - 场景适配” 四维协同架构。通过设计多元化榫卯互连结构、三层立体计算单元、功能导向型多元材料体系(兼容硅基及非硅)、血管化散热网络及标准化可重构模块,实现多芯片定制化适配。基于几何拓扑学、传热学理论推演及 32 篇权威文献交叉验证,该架构互连节点数量较传统 3D 集成提升 1 倍(互连自由度从 3 向拓展至 6 向),CPU/GPU/AI 芯片算力密度理论上分别达 28nm 平面芯片的 3 倍、4 倍、3.5 倍,研发周期可缩短 40%。本研究为后摩尔时代多芯片适配难题提供 “非技术突破型” 跨学科解决路径,其思想可延伸至立体光电、柔性电子等多场景,核心参数需后续实验校准(非理论逻辑缺陷)。本研究与专利 “一种榫卯力学特性启发的可重构多形态集成架构及自适应兼容转接方法”(中国专利申请号:2025118556570;专利回执号:10000552463749;申请日:2025.12.10)为同源创新,核心理论逻辑高度一致。

 

更新1 没错,这不仅仅是假说而是未来 (北京时间 15:22 2026-03-04)

之前我以为我这篇和脑机那篇论文由于是假说并没有多少人喜欢,因为太前沿了,太颠覆了,但随着这两天zenodo在补全下载数据,让我注意到这一篇的下载数据并不是个位数,而是21浏览47下载,甚至下载是浏览的2倍多,这让我意识到我这篇学界或者半导体领域学者都十分喜欢和重视。

在这里我需要说明下,这篇论文是我人生中第一篇论文,它是我走向独立研究者的开端,也是现在我拓展到动态系统,博弈论,传播论,视频领域,宇宙学以及未来或许更多领域的开端,因为特质锁定学论文是我从第三篇动态系统那篇提取的学科,因此从第四篇开始我就已经事实上掌握了在任意领域创作的钥匙,而其雏形,你们从这一篇应该能感受到,其将榫卯的力学结构反向迁移至半导体微观领域本身就是我的特质锁定学穿越表征直达本质的核心思想,尽管我的学科那时还没诞生,但你们依然能体会到其思维雏形。

而理解了这些之后,我在这里需要坦诚,从这篇标题,你们是否能感受到这是榫卯全栈系列第一篇,事实上我早已完成第二篇 (性能篇) 第三篇 (相当于指令集层级的篇章),而第二篇以28nm的传统芯片作为基准,那么我的榫卯结构芯片理论能达到192倍的性能,为什么如此夸张?是因为我的芯片由于是三维立体结构,因此本质性能提升是做乘法,而不是平面芯片做加法,因为我的芯片本质以16进制做基准进制,光从进制来说就比传统二进制本身有4倍性能提升,更别说其他方面了,而且我的性能增益仅仅是指物理或硬件层面的提升还没计算类似软件方面的睿频了,因此192倍性能提升你可以理解为无副作用的原生性能提升,那么如果用等效数量来形容的话,我的28nm榫卯结构芯片可以等效41.8颗目前的3nm制程芯片,这正是我榫卯架构的颠覆性所在:它不是在现有工艺上做优化,而是彻底重构了性能生成的底层逻辑,传统芯片在平面制程方面已经走到了尽头,而我的榫卯芯片仅仅是理论就已经秒杀所有目前芯片,即便考虑到工艺生产等多方面损耗,但落地后依然至少能保证有150-160倍以上的实际性能。那么采用更先进的14、7、5、3nm制程呢?

因此,我说我的榫卯芯片就是未来三维结构芯片的最优途径没有之一,是实际也没有夸张的说法,因为中国古建筑榫卯结构的成熟应用与工程验证已超 3000 年,其力学逻辑经数千年实践检验,稳定可靠,而比其更好的结构几乎可以说没有。至于为什么没有发布第二篇,因为我想得第一篇发布后有研究团队或者企业研究所之类的与我一同创作出可行的原型机,以28nm做出可行性的第一颗芯片,才有必要发表第二篇,不然毫无意义,而这里我只是在告诉大家我的芯片有多强,而一旦28nm芯片原型机完成,就可以继续攻克14nm 7nm 5nm等更先进的工艺。同时你们也注意到即使28nm原型机的成功,那么目前的英特尔 AMD 包括arm,苹果的m1 芯片等所有传统芯片都不会是我榫卯芯片的对手。

所以,如果你们或者感兴趣的企业或研究所,如果想要创造未来,那么我的榫卯芯片会是很好的方向,至少它会是你能看得见摸得着的,甚至能知道未来理论性能的新的架构,对比已经走到尽头的传统芯片来说,是朝阳,是希望。因为与其投入到性能微小差异的传统领域,不如投入到我榫卯芯片全新的开始,这会是最优且充满未来的方向,而第二篇(性能篇)只有原型机完成才会发布,那时将会对制造出原型机的团队或企业有质的股价或者价值估值的提升。

我是务实且重视落地的学者,每一篇论文都是高价值学术成果,即便太底层的理论短时间还没收到重视,但时间会证明一切,况且我自己也会写应用层的论文让其普及,如果你们对榫卯芯片感兴趣,那么欢迎联系我,我的邮箱一直都公布的。况且如果没人联系,也无所谓,因为半导体领域对我来说只是一小部分,而对于其从业者则是未来,因为我本身也是原理0-1的理论构建者,而我是兴趣导向,对我来说有很多且更有意思的领域等着我去挖掘呢。那么榫卯芯片是否能落地不取决于我,而取决于你(企业,研究所,团队等)。

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Mortise and Tenon Full Stack 1_ An Innovative Concept of Multi-Chip Integration Based on Mechanical Properties of Mortise and Tenon in the Post-Moore Era - Framework Construction and Adaptation Optimization_English.pdf

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Additional details

Additional titles

Alternative title (Mandarin Chinese)
榫卯全栈 1:后摩尔时代基于榫卯力学特性的多芯片集成创新构想 —— 框架构建与适配优化

Identifiers

DOI
10.6084/m9.figshare.30937691.v4

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