DESIGN OF LOW POWER 9T SRAM CELL WITH EXPANDED NOISE MARGIN

SRAM (Static random access memory) cells operate at lower power supply voltages with higher stability got major attention due to their utmost demand in advanced microelectronics devices. In scaled technologies, the power dissipation and stability of SRAM cells become of prime importance due to the aggressive supply voltage scaling. In this context, a novel 9T SRAM memory cell has been proposed with a commendable improvement in both read stability and write stability of the cell along with a reduction in power dissipation. The characteristics parameters of the proposed 9T SRAM cell are compared with state of-the-art designs like six transistors (6T), tunable access transistors 8T (TA8T), D2P11T (data dependent power supply 11T), and 11T SRAM cells. The RSNM (read static noise margin) of the novel proposed 9T SRAM cell is enhanced by 1.95×, 1.92×, 1.87×, 1.90× as of 6T, TA8T, D2P11T and 11T SRAM cells respectively. It occurs as a result by utilization of an isolated read port during read operation. Further, the write ability of the proposed 9T SRAM cell is increased by 1.12×, 1.05×, 1.12×, 1.14× as of 6T, TA8T, D2P11T and 11T SRAM cells respectively. The read power of 9T SRAM cells also gets reduced by 1.48×,1.16×, 1.38×, 1.66× as of 6T, TA8T, D2P11T, 11T SRAM cells. In addition to this, read access time of the proposed 9T cell is reduced by 1.08×, 1.01×, 1.04×. 1.15× as of 6T, TA8T, D2P11T, 11T SRAM cells. In proposed 9T cell, the I_on to I_off ratio is larger, i.e., 3.5×, 3.45×, 3.54×, as compared to 6T, TA8T, 11T SRAM cells. It shows the applicability of a 9T SRAM cell for a large density array. The simulation work has been performed with Cadence Virtuoso at the 45nm technology node.