Fault Injection Attacks Based on Layout-Driven SER Analysis

The ongoing downscaling of CMOS technology has considerably increased the vulnerability of Integrated Circuits (ICs) to reliability issues, such as Soft Errors and Hardware Trojans (HTs). The combined impact of these threats poses an even more significant challenge to circuit security. The study of the Single Event Multiple Transients (SEMTs) generation and propagation through the circuits constitute the most critical process of the proposed methodology. In particular, a comprehensive layout-based analysis is presented to identify the most impactful regions (grids) in a circuit where HTs can be intentionally injected. Experimental outcomes demonstrate a significant average increase of approximately 32% in the Soft Error Rate (SER) of the utilized ISCAS ’89 benchmarks, highlighting the need for a more robust system design to combat reliability-based threats.