Published May 30, 2025 | Version CC-BY-NC-ND 4.0

Floating Point Unit with High Precision Efficiency

  • 1. Assistant Professor, Department of Electronics and Communication Engineering, DSATM, Bangalore (Karnataka), India.

Contributors

Contact person:

  • 1. Assistant Professor, Department of Electronics and Communication Engineering, DSATM, Bangalore (Karnataka), India.
  • 2. Associate Professor, Department of Electronics and Communication Engineering, KSIT, Bangalore (Karnataka), India.

Description

Abstract: In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning—our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbers get bigger. For multiplication, we turn to the radix-4 Booth multiplier. This powerhouse streamlines the multiplication process by cutting down the number of partial products and operations needed, efficiently handling both positive and negative numbers. By integrating these components, our FPU can handle floating-point arithmetic with excellent efficiency and reliability. In scientific computing, this means more accurate simulations and data analyses. For graphics processing, it translates to better image rendering and smoother visual effects. And in machine learning, itsupportsrobust training and execution of algorithms on massive datasets, ensuring dependable model performance.

Files

B366915020525.pdf

Files (876.7 kB)

Name Size Download all
md5:beb87894c7de21e4e7e987ca40bd3d45
876.7 kB Preview Download

Additional details

Identifiers

Dates

Accepted
2025-05-15
Manuscript Received on 24 April 2025 | First Revised Manuscript Received on 28 April 2025 | Second Revised Manuscript Received on 06 May 2025 | Manuscript Accepted on 15 May 2025 | Manuscript published on 30 May 2025.

References

  • Vasudeva G., Uma B. V., "Low Voltage Low Power and High Speed OPAMP Design using High-K FinFET Device," WSEAS Transactions on Circuits and Systems, vol. 20, pp. 80-87, 2021, DOI: http://doi.org/10.37394/23201.2021.20.11
  • N. A. S. Adela, A. N. B. Yousuf and M. M. Eljhani, "Design and Implementation of Single Precision Floating-point Arithmetic Logic Unit for RISC Processor on FPGA," 2023 IEEE 3rd International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering (MI-STA), Benghazi, Libya, 2023, pp. 130-134, DOI: http://doi.org/10.1109/MI-STA57575.2023.10169623
  • Daphni, Samraj & Grace, Kasinadar. (2019). Design and Analysis of 32- Bit Parallel Prefix Adders for Low Power VLSI Applications. Advances in Science, Technology and Engineering Systems Journal. 4. DOI: http://doi.org/10.25046/aj040213
  • Dr. S V Viraktimath, Khushi S A, Vaishnavi P, W Wiranchi. "Analysis of Parallel Prefix Adders." International Journal for Research in Applied Science & Engineering Technology (IJRASET) ISSN: 2321- 9653; IC Value: 45.98; SJ Impact Factor: 7.538 Volume 11 Issue XII Dec 2023, https://www.ijraset.com/best-journal/analysis-of-parallel-prefixadders.
  • Asif, Shahzad & Kong, Yinan. (2015). "Performance Analysis of Wallace and Radix-4 Booth-Wallace Multipliers." June 2015 Conference: Electronic System Level Synthesis Conference (ESLsyn), https://www.researchgate.net/publication/301328842_Performance_A nalysis_of_Wallace_and_Radix-4_Booth-Wallace_Multipliers
  • Athihrii, M. Stephen and S. Kumar, "Design and implementation of 32- bit ALU using Verilog," 02 June 2016. https://www.researchgate.net/publication/372170624_Design_and_Im plementation_of_Single_Precision_Floatingpoint_Arithmetic_Logic_Unit_for_RISC_Processor_on_FPGA
  • D. Malik and R. S. Rathore, "32-bit Arithmetic Logical Unit (ALU) using VHDL," vol. 1, no. 1, 26 NOV 2013. https://www.ijset.in/wpcontent/uploads/2014/02/IJSET101100082013.pdf
  • R. Cherian, N. Thomas and Y. Shyju, "Implementation of Binary to Floating Point Converter using HDL," no. 461-64, 2013. https://www.researchgate.net/publication/372170624_Design_and_Im plementation_of_Single_Precision_Floatingpoint_Arithmetic_Logic_Unit_for_RISC_Processor_on_FPGA
  • R. Payal, "Simulation and Synthesis Model for the Addition of Single Precision Floating Point Numbers Using Verilog," vol. 02, no. 09 Sep 2013. https://www.researchgate.net/publication/372170624_Design_and_Impl ementation_of_Single_Precision_Floatingpoint_Arithmetic_Logic_Unit_for_RISC_Processor_on_FPGA
  • Vasudeva G., Uma B. V., "Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET," WSEAS Transactions on Systems and Control, vol. 17, pp. 1-15, 2022, DOI: http://doi.org/10.37394/23203.2022.17.1
  • Vasudeva G, Uma B V, "Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology", International Journal of Electrical and Computer Engineering (IJECE), vol. 12, no. 2, ISSN: 2088-8708, v12i2, pp. 2158- 2168, April 2022. DOI: http://dx.doi.org/10.11591/ijece.v12i2.pp2158-2168
  • D, Divya., Balasaraswathi, M, R., Harini kalyani, & I, V. Anand. (2020). Modelling and Execution of Floating Point Parallel Processing Operation for RISC Processor. In International Journal of Engineering and Advanced Technology (Vol. 9, Issue 3, pp. 3783–3789). DOI: https://doi.org/10.35940/ijeat.c6203.029320
  • Jency Rubia J, Sathish Kumar G.A, FIR Filter Design using Floating Point Column Bypassing Technique. (2019). In International Journal of Recent Technology and Engineering (Vol. 8, Issue 2S4, pp. 409–413). DOI: https://doi.org/10.35940/ijrte.b1079.0782s419
  • Honade, Dr. S. J. (2019). Low Power 32-Bit Floating Point Adder/Subtractor Design using 50nm CMOS VLSI Technology. In International Journal of Innovative Technology and Exploring Engineering (Vol. 8, Issue 10, pp. 662–674). DOI: https://doi.org/10.35940/ijitee.j8788.0881019