The NEORV32 RISC-V Processor

What's Changed

• Rework caches; use "write-through" strategy by @stnolting in https://github.com/stnolting/neorv32/pull/1259
• Rework locking of processor-internal bus by @stnolting in https://github.com/stnolting/neorv32/pull/1260
• minor edits and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1262
• ✨ add cache burst transfers by @stnolting in https://github.com/stnolting/neorv32/pull/1263
• [bus] add explicit burst signal to internal processor bus by @stnolting in https://github.com/stnolting/neorv32/pull/1265
• 🐛 Fix missing burst signal in bus register stage by @stnolting in https://github.com/stnolting/neorv32/pull/1266
• ⚠️ make MCAUSE CSR read-only by @stnolting in https://github.com/stnolting/neorv32/pull/1267
• ⚠️ [inter-processor communication] remove hardware spinlocks and inter-core communication links by @stnolting in https://github.com/stnolting/neorv32/pull/1268
• :bug: fix CPU bus issues by @stnolting in https://github.com/stnolting/neorv32/pull/1270

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.4...v1.11.5