Low-Power Reconfigurable FIR Filter HDL Design

This article discusses the process of HDL (hardware description language) design and testing of reconfigurable FIR filter optimized for low-power consumption in  nanoscale CMOS technology. The maximum number of coefficients and used numerical data representation can be set during synthesis. The end-user is then capable of changing the number of active coefficients (filter order) and their value. All flip-flops can be rearranged into 1-bit scan-chain for production test and it can also be used for filter debugging. MATLAB application was developed for easier interaction with the FIR filter. It allows to set the coefficients, process the samples, scan and display the contents of flip-flops.