A formally-verified Network-on-Chip in Coq

This thesis presents a formally-verified Network-on-Chip (NoC) library implemented in
Coq, aimed at improving the trustworthiness of communication architectures. Due to the
diminishing returns of transistor scaling, System-on-Chips (SoCs) have become the preferred
method for building high-performance chips. Inter-core communication is often facilitated
by a communication subsystem known as NoC. However, verifying the correctness of NoCs
remains a significant challenge because of their large state space and configurable parameters.
This work introduces a novel approach that leverages Kôika, an embedded domain-specific
language in Coq, to generate NoCs with formal guarantees. The thesis explores the use of
metaprogramming and dependent programming to generalize these NoCs, enabling designs of
arbitrary sizes with formal correctness proofs. The proposed library aims to reduce verification
overhead by proving properties over generic instances, thus eliminating the need to verify every
instance of NoC separately. Kôika ’s formally-verified compiler generates the NoC’s Verilog
code, which is synthesized to obtain expected hardware resource characteristics.