RISC++: A 32-bit RISC-V Core via High-Level Synthesis of C/C++

As hardware design shifts towards custom architectures, custom-made Central Processing Units (CPUs) emerge as a mechanism to provide more efficient hardware amidst evergrowing demand. However, the traditional design process may introduce difficulties when the Instruction Set Simulator (ISS) and the Hardware Description Language (HDL) code are defined in different abstraction levels, and not intrinsically correlated. This may lead to divergences between these two components of the design, slowing production down. A more efficient method for the development of these systems is possible through High-level Synthesis (HLS), where a program written in a high-level programming language can be converted into HDL. With this in mind, we propose the creation of a C/C++ codebase that serves for instruction set simulation and also for HLS. This method may avoid production problems and considerably reduce necessary hardware developer expertise when creating a custom RISC-V CPU, without compromising the end product.