The NEORV32 RISC-V Processor

What's Changed

• [rtl] reset SDA and SCL of TWI and TWD to '1' by @LukasP46 in https://github.com/stnolting/neorv32/pull/1167
• ⚠️ rename JEDEC ID generic; minor rtl edits and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1168
• 🐛 fix BOOTROM addressing by @stnolting in https://github.com/stnolting/neorv32/pull/1171
• 🐛 Fix crt0's main entry address being overridden by constructors by @stnolting in https://github.com/stnolting/neorv32/pull/1172
• Minor rtl optimizations and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1174
• ⚠️ remove execute in-place (XIP) module by @stnolting in https://github.com/stnolting/neorv32/pull/1175
• [cfs] Add missing CFS clock gen enable signal. by @Sazzach in https://github.com/stnolting/neorv32/pull/1177
• ✨ add memory coherency logic by @stnolting in https://github.com/stnolting/neorv32/pull/1176
• Doc ds fixes by @DAR0001 in https://github.com/stnolting/neorv32/pull/1178
• [docs] SPI: minor fixes by @stnolting in https://github.com/stnolting/neorv32/pull/1166
• Minor rtl edits and cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/1179
• :warning: rename UART RTS/CTS signals by @stnolting in https://github.com/stnolting/neorv32/pull/1180

New Contributors

• @Sazzach made their first contribution in https://github.com/stnolting/neorv32/pull/1177
• @DAR0001 made their first contribution in https://github.com/stnolting/neorv32/pull/1178

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.11.0...v1.11.1