Published February 28, 2025 | Version CC-BY-NC-ND 4.0
Journal article Open

An Efficient AES Design and Implementation Using FPGA

Authors/Creators

  • 1. Senior Student, Department of Electronics and Communication Engineering, Faculty of Engineering, Mansoura University, Egypt.

Contributors

  • 1. Senior Student, Department of Electronics and Communication Engineering, Faculty of Engineering, Mansoura University, Egypt.
  • 2. Associate Professor, Department of Electronics and Communication Engineering, Faculty of Engineering, Mansoura University, Egypt.

Description

Abstract: The more technology develops, the greater the amount of digital information. This requires that information be secure and free from hacking, so we use encryption algorithms. One of the most famous is the Advanced Encryption Standard (AES). This paper deals with the hardware implementation of the AES Rijndael Encryption Algorithm using Xilinx Virtex-6 & Artix-7 FPGA. The work aims for a balanced design between speed, area, and power. The S-Box hardware design is based on pre-calculated look-up tables (LUTs). This method is characterized by less time and less architectural complexity. The mix-column transformations are calculated by shift and XOR methods. The encryption block is efficiently designed using Verilog-HDL and synthesized on a Virtex-6 chip (Target Device) with the help of Xilinx ISE Design Suite 14.7 Tool. The proposed architecture has good results regarding throughput, area, and power.

Files

E95060412523.pdf

Files (1.1 MB)

Name Size Download all
md5:b870fc116adfa6dbbaebc1af07f72622
1.1 MB Preview Download

Additional details

Identifiers

DOI
10.35940/ijese.E9506.13030225
EISSN
2319-6378

Dates

Accepted
2025-02-15
Manuscript received on 18 March 2023 | First Revised Manuscript received on 02 January 2025 | Second Revised Manuscript received on 18 January 2025 | Manuscript Accepted on 15 February 2025 | Manuscript published on 28 February 2025.

References

  • JNNCE Journal of Engineering & Management, Volume 4, No.1, January – June 2020 -Implementation of AES Algorithm Using Verilog Ganesh Gopal Shet, Jamuna V, Shravani S, Nayana H G, Pramod Kumar S J N N College of Engineering, Shimoga. https://typeset.io/pdf/implementation-of-aes-algorithm-using-verilog1uuuwecb45.pdf
  • B. A. Forouzan, "Advanced encryption techniques," in Cryptography and Network Security, 2015, pp. 191–220, McGraw-Hill Education. https://almuhammadi.com/sultan/books_2020/Forouzan.pdf
  • National Institute of Standards and Technology, "Announcing the Advanced Encryption Standard (AES) (FIPS Publication 197)," U.S. Department of Commerce, 2001. https://csrc.nist.gov/pubs/fips/197/final
  • Chellam, M.B. and Natarajan, R. (2018), "AES hardware accelerator on FPGA with improved throughput and resource efficiency", Arabian Journal for Science and Engineering, Vol. 43 No. 12, pp. 6873-6890. DOI: https://doi.org/10.1007/s13369-017-2925-0
  • Wang, Y. and Ha, Y. (2013), "FPGA-based 40.9-gbits/s masked AES with area optimization for storage area network", IEEE Trans. Circ. Syst. II: Express Briefs, Vol. 60 No. 1, pp. 36-40. DOI: https://ieeexplore.ieee.org/abstract/document/6472789
  • Oukili, S. and Bri, S. (2017), "Hardware implementation of AES algorithm with logic S-box", J. Circuits, Systems, and Computers, Vol. 26 No. 9. DOI: https://doi.org/10.1142/S0218126617501419
  • Shanthi Rekha, S. and Saravanan, P. (2019), "Low-Cost AES-128 implementation for edge devices in IoT applications", Journal of Circuits, Systems, and Computers, Vol. 28 No. 4, p. 1950062. DOI: https://doi.org/10.1142/S0218126619500622
  • P., R. and H., M. (2021), "Design and implementation of power and area optimized AES architecture on FPGA for IoT application", Circuit World, Vol. 47 No. 2, pp. 153-163. DOI: https://www.emerald.com/insight/content/doi/10.1108/cw-04-2019- 0039/full/pdf
  • Lakshminarayana, G., Deshpande, Dr. A. A., & Babu, Dr. M. G. (2019). Design of High Speed Advanced Encryption Standard using PPA and PPM. In International Journal of Innovative Technology and Exploring Engineering (Vol. 8, Issue 9, pp. 2679–2684). DOI: https://doi.org/10.35940/ijitee.i8989.078919
  • Satyanarayana*, B., & Srinivasan, D. M. (2019). Advanced Encryption Standard for Data Encryption using EDK Environment in FPGA. In International Journal of Recent Technology and Engineering (IJRTE) (Vol. 8, Issue 4, pp. 11969–11972). DOI: https://doi.org/10.35940/ijrte.d9920.118419
  • Murugan M, S., & Sasilatha, Dr. T. (2019). Hardware Implementation of Hybrid Model Encryption Algorithm for Secure Transmission of Medical Images. In International Journal of Engineering and Advanced Technology (Vol. 9, Issue 1s, pp. 164–167). DOI: https://doi.org/10.35940/ijeat.a1042.1091s19