The NEORV32 RISC-V Processor

What's Changed

• 🧪 Shrink bootloader ISA and RAM requirements by @stnolting in https://github.com/stnolting/neorv32/pull/1118
• [sim] rework default testbench by @stnolting in https://github.com/stnolting/neorv32/pull/1119
• ⚠️ rework TRNG by @stnolting in https://github.com/stnolting/neorv32/pull/1120
• ✨ add new module: device-mode I²C controller ("TWD") by @stnolting in https://github.com/stnolting/neorv32/pull/1121
• Docs: removed Chapter about VHDL Development Environment by @vogma in https://github.com/stnolting/neorv32/pull/1122
• 🧪 [pmp] use time-multiplex approach by @stnolting in https://github.com/stnolting/neorv32/pull/1105
• minor rtl cleanups and optimization by @stnolting in https://github.com/stnolting/neorv32/pull/1123
• Relocate clock gating switch by @stnolting in https://github.com/stnolting/neorv32/pull/1124
• ⚠️ Rename CPU tuning options / generics by @stnolting in https://github.com/stnolting/neorv32/pull/1125
• ⚠️ Rework IO/peripheral address space by @stnolting in https://github.com/stnolting/neorv32/pull/1126

New Contributors

• @vogma made their first contribution in https://github.com/stnolting/neorv32/pull/1122

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.7...v1.10.8