Published November 30, 2021 | Version v1
Journal article Open

Machine Learning for Next-Generation Power, Performance, and Area Optimization in Semiconductor Design

Description

Power, Performance, and Area (PPA) optimization is a critical aspect of modern semiconductor design, driven by the demand for efficiency and compactness in electronic devices. Traditional methods rely on exhaustive, iterative processes that are both time-consuming and resource-intensive. This paper explores the application of machine learning (ML) to transform PPA optimization by leveraging advanced predictive models trained on extensive historical design data. The proposed approach achieved a remarkable power prediction accuracy of 94.6%, performance prediction accuracy of 92.8%, and area prediction accuracy of 90.5%, significantly surpassing traditional methods. Additionally, ML-driven optimization reduced design iterations by 75%, from 20 to 5, and optimization time by nearly 80%, from 48 hours to just 10 hours. Deviations from target values were minimized, with power, area, and performance deviations reduced to 1.8%, 2.3%, and 1.6%, respectively. These results demonstrate the transformative potential of ML in automating and refining PPA optimization, enabling faster, more precise, and resource-efficient design processes for future advancements in semiconductor technology.

Files

EJAET-8-11-137-147.pdf

Files (529.5 kB)

Name Size Download all
md5:065b578730633f8a7d7f5187514f1c5f
529.5 kB Preview Download

Additional details

References

  • [1]. Moore, G. E. (1965). Cramming more components onto integrated circuits. Electronics, 38(8), 114–117.
  • [2]. Guthaus, M. R., et al. (2016). OpenRAM: An open-source memory compiler. Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 93:1–93:6.
  • [3]. Elfadel, I. A. M., et al. (2018). Machine Learning in VLSI Computer-Aided Design. Springer.
  • [4]. Lyu, W., et al. (2018). Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design. ICML.
  • [5]. Liao, T., et al. (2017). Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits. ASP-DAC.
  • [6]. Wang, H., et al. (2018). Learning to design circuits. NeurIPS Machine Learning for Systems Workshop.
  • [7]. Chaudhuri, S., & Jha, N. K. (2014). FinFET logic circuit optimization with different FinFET styles. 27th International Conference on VLSI Design.
  • [8]. Brown, A. R., et al. (2013). Comparative simulation analysis of process-induced variability in nanoscale SOI and bulk trigate FinFETs. IEEE Transactions on Electron Devices, 60(11), 3611–3617.
  • [9]. Sylvester, D., & Kaul, H. (2001). Power-driven challenges in nanometer design. IEEE Design & Test, 18(6), 12–22.
  • [10]. Wang, L., & Luo, M. (2019). Machine learning applications and opportunities in IC design flow. 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1–3.
  • [11]. S. Banerjee et al., "A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration," arXiv preprint, arXiv:2111.15024, 2020.
  • [12]. H. Esmaeilzadeh et al., "VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis," Proceedings of ICCAD, 2021, pp. 1–8.
  • [13]. H. Genc et al., "Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration," Proceedings of DAC, 2021, pp. 769–774.
  • [14]. D. Mahajan et al., "TABLA: A Unified Template-Based Framework for Accelerating Statistical Machine Learning," Proceedings of HPCA, 2016, pp. 14–26.
  • [15]. T. Moreau et al., "A Hardware–Software Blueprint for Flexible Deep Learning Specialization," IEEE Micro, 39(5), 2019, pp. 8–16.
  • [16]. E. Tabanelli et al., "DNN Is Not All You Need: Parallelizing Non-Neural ML Algorithms on Ultra-Low-Power IoT Processors," arXiv preprint, arXiv:2107.09448, 2021.
  • [17]. S. Mittal, "A Survey of Techniques for Approximate Computing," ACM Computing Surveys, 48(4), 2016.
  • [18]. V. K. Chippa et al., "Scalable Effort Hardware Design," IEEE Transactions on VLSI Systems, 22(9), 2014, pp. 2004–2016.
  • [19]. M. Shafique et al., "TinyML: Current Progress, Research Challenges, and Future Roadmap," Proceedings of DAC, 2021, pp. 1303–1306.
  • [20]. Wang, M., Lv, W., Yang, F., Yan, C., Cai, W., Zhou, D., & Zeng, X. (2018). Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(10), 1929–1942.
  • [21]. Yao, J., Ye, Z., & Wang, Y. (2015). An Efficient SRAM Yield Analysis and Optimization Method with Adaptive Online Surrogate Modeling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(7), 1245–1253.
  • [22]. N. Horta. (2002). Analogue and mixed-signal systems topologies exploration using symbolic methods. AICSP.
  • [23]. E. Deniz et al. (2010). Hierarchical performance estimation of analog blocks using Pareto fronts. 6th Conference on Ph.D. Research in Microelectronics Electronics.
  • [24]. Kipf, T. N., & Welling, M. (2016). Semi-Supervised Classification with Graph Convolutional Networks. arXiv preprint arXiv:1609.02907.
  • [25]. G. Zhang et al. (2019). Circuit-GNN: Graph Neural Networks for Distributed Circuit Design. Proceedings of ICML.
  • [26]. Chen, G., Chen, W., Ma, Y., Yang, H., & Yu, B. (2020). DAMO: Deep Agile Mask Optimization for Full Chip Scale. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
  • [27]. Ye, W., Alawieh, M. B., Lin, Y., & Pan, D. Z. (2019). LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks. Proceedings of ACM/IEEE Design Automation Conference (DAC).
  • [28]. Wagner, I., Bertacco, V., & Austin, T. M. (2007). Microprocessor Verification via Feedback-Adjusted Markov Models. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 26(6), 1126–1138.
  • [29]. Kahng, A. B., Lin, B., & Nath, S. (2015). ORION3.0: A Comprehensive NoC Router Estimation Tool. IEEE Embedded Systems Letters, 7(2), 41–45.
  • [30]. Lee, W., Kim, Y., Ryoo, J. H., Sunwoo, D., Gerstlauer, A., & John, L. K. (2015). PowerTrain: A Learning-Based Calibration of McPAT Power Models. Proc. ISLPED, 189–194.
  • [31]. Greathouse, J. L., & Loh, G. H. (2018). Machine Learning for Performance and Power Modeling of Heterogeneous Systems. Proc. ICCAD, 1–6.
  • [32]. Lin, Z., Zhao, J., Sinha, S., & Zhang, W. (2020). HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. Proc. ASP-DAC, 574–580.
  • [33]. Zhang, Y., Ren, H., & Khailany, B. (2020). Grannite: Graph Neural Network Inference for Transferable Power Estimation. Proc. DAC, 1–6.
  • [34]. Xu, P., Zhang, X., Hao, C., Zhao, Y., Zhang, Y., Wang, Y., et al. (2020). AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. Proc. FPGA, 40–50.
  • [35]. Kwon, J., & Carloni, L. P. (2020). Transfer Learning for Design-Space Exploration with High-Level Synthesis. Proc. MLCAD, 163–168.
  • [36]. Ullah, S., Schmidl, H., Sahoo, S. S., Rehman, S., & Kumar, A. (2021). Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures. IEEE Transactions on Computers, 70(3), 384–392.
  • [37]. Last, F., Haeberlein, M., & Schlichtmann, U. (2020). Predicting Memory Compiler Performance Outputs Using Feed-Forward Neural Networks. ACM Transactions on Design Automation of Electronic Systems, 25(5), 1–15.