The NEORV32 RISC-V Processor

What's Changed

• [rtl] signal renamings and cleanups to make the code more readable by @stnolting in https://github.com/stnolting/neorv32/pull/1026
• :bug: fix minor bug in FPU MUL instruction by @stnolting in https://github.com/stnolting/neorv32/pull/1028
• [rtl] remove redundant prog_buf by @NikLeberg in https://github.com/stnolting/neorv32/pull/1030
• [rtl] fix generate spelling by @NikLeberg in https://github.com/stnolting/neorv32/pull/1031
• [cpu] rework ALU instruction decoding and CPU co-processor interface by @stnolting in https://github.com/stnolting/neorv32/pull/1032
• ✨ [cpu] add support for RISC-V scalar cryptography ISA extensions by @stnolting in https://github.com/stnolting/neorv32/pull/1033
• Fix typo trap table by @BEforlin in https://github.com/stnolting/neorv32/pull/1035
• Add Zkt ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1036
• :sparkles: add support for RISC-V Zbkb ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1037
• ✨ add support for RISC-V Zbkc ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1038
• Add Zkn ISA extension by @stnolting in https://github.com/stnolting/neorv32/pull/1039
• ✨ add support for RISC-V Zks* ISA extensions by @stnolting in https://github.com/stnolting/neorv32/pull/1040
• ⚠️ Rename CPU ISA configuration generics by @stnolting in https://github.com/stnolting/neorv32/pull/1041
• :warning: split B ISA extension into individual sub-extensions by @stnolting in https://github.com/stnolting/neorv32/pull/1044

New Contributors

• @BEforlin made their first contribution in https://github.com/stnolting/neorv32/pull/1035

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.4...v1.10.5