The NEORV32 RISC-V Processor

What's Changed

• minor RTL cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1004
• 🧪 Remove "loop" from memory initialization function by @stnolting in https://github.com/stnolting/neorv32/pull/1005
• minor fixes in OCD by @NikLeberg in https://github.com/stnolting/neorv32/pull/1006
• [sw] fix sysinfo doxygen header by @NikLeberg in https://github.com/stnolting/neorv32/pull/1007
• optimize CSR address logic by @stnolting in https://github.com/stnolting/neorv32/pull/1008
• Minor rtl/CSR optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1010
• Cleanup debug symbols by @stnolting in https://github.com/stnolting/neorv32/pull/1009
• minor HDL cleanups and otimizations by @stnolting in https://github.com/stnolting/neorv32/pull/1014
• Cleanup and extend watch dog's reset-cause logic by @stnolting in https://github.com/stnolting/neorv32/pull/1015
• ⚠️ Refactor RTL files / hierarchy by @stnolting in https://github.com/stnolting/neorv32/pull/1017
• :bug: fix B.CTZ decoding regression bug by @stnolting in https://github.com/stnolting/neorv32/pull/1018
• Massive rtl code cleanup by @stnolting in https://github.com/stnolting/neorv32/pull/1019
• :bug: fix stack alignment upon first procedure entry by @stnolting in https://github.com/stnolting/neorv32/pull/1021

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.10.3...v1.10.4