ELECTRONICS & ELECTRICAL DOMAIN
Published September 10, 2024 | Version v1
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A Comprehensive Approach to Maximize Efficiency with a High-Performance Flip-Flop for Low-Power Applications

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This research introduces a novel approach to tackle leakage power in digital circuits, focusing on D flip-flops crucial for various applications. We propose a pioneering design incorporating an enhanced sub-threshold Voltage Level (SVL) technique, aimed at reducing standby power consumption. Through comprehensive simulation using Tanner T Spice at the 45nm technology node, our design achieves an impressive 60.54% reduction in the power delay product compared to existing designs. By minimizing leakage currents and optimizing clocked transistor usage, our approach presents a promising solution for enhancing power efficiency in D flip-flops. This advancement mark a significant step forward in low-power digital circuit design, offering practical benefits for energy-conscious applications.

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References

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