Published September 9, 2024 | Version v1
Journal article Open

Design of MUX Based Circuit for Half Adder and Half Subtractor

Description

This study delves into crafting a circuit that seamlessly performs both half addition and half subtraction. Leveraging two 2:1 Multiplexers, an XOR gate, and NOT gates, the design achieves dual functionalities while optimizing component usage. A control signal dictates the operational mode, ensuring adaptability with a straightforward assembly of common components. While this integrated circuit offers a compact and versatile solution for fundamental arithmetic operations, it's primarily suited for single-bit tasks and necessitates an extra control signal.

Files

Design of MUX Based Circuit For Half Adder And Half Subtractor.pdf

Files (233.9 kB)

Additional details

References

  • 1. Digital logic and computer design by M. MORRIS MANO twenty second impression2024.
  • 2. Analysis of various approximate adders in ripple carry adder design.2023.
  • 3. Design of energy efficient static level restorer based half subtractor using CNFETs.2022.
  • 4. Design of three valued logic half subtractor using GNRFET.2022.
  • 5. 2:1 MUX design using multitudinous logic families at 45nm technology.2021.
  • 6. Design and implementation of high speed hybrid carry select adder.2021.
  • 7. John F. Wakerly, Digital Design: Principles and Practices, Pearson, 5th Edition, 2021.
  • 8. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, McGraw-Hill, 3rd Edition, 2019.
  • 9. Neil H. E. Weste, CMOS VLSI Design: A Circuits and Systems Perspective, Addison-Wesley, 4th Edition, 2018.
  • 10. Rabaey, J. M., Digital Integrated Circuits: A Design Perspective, Prentice Hall, 2nd Edition, 2008.