ELECTRONICS & ELECTRICAL DOMAIN
Published September 6, 2024 | Version v1
Journal article Open

VLSI Design and Verification of a Multi-Function Arithmetic Logic Unit

Authors/Creators

Description

Exploring an ALU Design in the VLSI Domain - Within modern processors like CPUs, FPUs, and GPUs, the Arithmetic Logic Unit (ALU) serves as a critical building block. In this review paper, we delve into the Very Large Scale Integration (VLSI) design of an ALU, exploring its functionality through meticulous simulation and testing. Leveraging the Xilinx ISE design suite 14.7, the study validates the proposed ALU's gate-level and chip-level implementation, ensuring its ability to execute nine essential operations: addition, subtraction, multiplication, shifting, comparison, AND, OR, NOT, and XOR. (comparison between existing and new proposed design).

Files

VLSI Design and Verification of a Multi-function Arithmetic Logic Unit.pdf

Files (432.0 kB)

Additional details

References

  • 1. Samaiya, S., & Jain, A. (2018). A review article of FPGA ALU unit design based on GA. International journal of scientific research and engineering trends, 4(4).
  • 2. "Digital comparator", Wikipedia. Reddy, G. K. (2015, January). Low power-area Pass Transistor Logic based ALU design using low power full adder design. In 2015 IEEE 9th International Conference on Intelligent Systems and Control (ISCO) (pp. 1-6). IEEE.
  • 3. Ravindran, N., & Lourde, R. M. (2015, May). An optimum VLSI design of a 16-BIT ALU. In 2015 International Conference on Information and Communication Technology Research (ICTRC) (pp. 52-55). IEEE.
  • 4. Surekha, G., Madesh, G., Kumar, M. P., & Sriramoju, H. (2023, May). Design and Implementation of Arithmetic and Logic Unit (ALU). In 2023 2nd International Conference on Applied Artificial Intelligence and Computing (ICAAIC) (pp. 1530-1536). IEEE.
  • 5. Surekha, G., Madesh, G., Kumar, M. P., & Sriramoju, H. (2023, May). Design and Implementation of Arithmetic and Logic Unit (ALU). In 2023 2nd International Conference on Applied Artificial Intelligence and Computing (ICAAIC) (pp. 1530-1536)IEEE.
  • 6. Gadda, N., & Eranna, U. (2020, February). 64-bit ALU design using vedic mathematics. In 2020 international conference on emerging trends in information technology and engineering (ic-ETITE) (pp. 1-4). IEEE.
  • 7. Kahar, D. K., & Mehta, H. (2017, June). High speed vedic multiplier used vedic mathematics. In 2017 International Conference on Intelligent Computing and Control Systems (ICICCS) (pp. 356-359). IEEE.
  • 8. Palnitkar, S. (2003). Verilog HDL: a guide to digital design and synthesis (Vol. 1). Prentice Hall Professional.
  • 9. Sarangi S., Swain S.(2022). VHDL implementation of Arithmetic logic unit. International Journal of Engineering Research & Technology (IJERT).3(4).
  • 10. Khurana, S., & Kaur, K. (2012). Implementation of ALU using FPGA. International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), 1(2), 146-149.