Online Degradation Detection and Estimation of SiC Power MOSFET based on TSEP

This paper introduces an approach for the degradation estimation of power semiconductor devices by jointly considering multiple temperature-sensitive electrical parameters. Specifically, threshold voltage and gate peak current of silicon-carbide power MOSFET are combined as chip-related health indicator signals. A neural network is then employed to map these signals to an aging state, and data series are utilized to improve the degradation estimation process. Experimental results demonstrate the effectiveness of the proposed method, showing that it enables degradation estimation with a maximal mean absolute percentage error of 11.85%. Consequently, the proposed method allows detection of degradation evolution during the operation of the converter without measuring the junction temperature.