A Novel Design of Low-Power High-Speed Double Tail Dynamic Latch Comparator with SAPON Tail Latch

his paper presents a novel design of low-power high-speed
double-tail dynamic latch comparator with SAPON tail latch.
Comparators are among the key components in such systems which
include zero crossing detectors, data acquisition circuits, and data
converters like Analog-to-Digital Convertors (ADCs). All modern
devices employing Latch Comparator (LC) should be efficient in terms
of speed and power. Dynamic Latch Comparator (DLC) is one of the
solutions for such efficient applications. Therefore, in this paper, a
novel design of low-power high-speed double-tail dynamic latch
comparator (DTDLC) is proposed with SAPON tail latch. Simulation
is done with Mentor Graphics’ Tanner EDA tools v2019.2 using 45nm
CMOS technology. The proposed DTDLC design when operated with
1.0V supply and 100MHz clock frequency, shows a power consumption
of 3.005 µWatt (which illustrates a 90.21% reduction) with time delay
(clock-to-output) of 20.69 n-sec (which is 0.86% less) & PDP of 62.07
f-joule (which is 90.3% less) compared to that of a conventional
DTDLC design. To verify the superiority of our proposed design in
DTDLCs, existing DTDLCs are also simulated with same technology
and a table is drawn for performance analysis based on parameters of
power consumption, time delay, power-delay-product (PDP), and area
(in terms of number of transistors used).