Design and Implementation of Comparator circuit using Advanced Logic Technologies
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In the ever-evolving landscape of digital systems, the need for efficient and high-performance comparators has become increasingly vital. This paper presents the design and implementation of an N-bit comparator circuit, where N represents the number of bits for comparison. The comparator is a crucial component in digital systems, finding applications in areas such as arithmetic operations, data sorting, and decision-making processes. The proposed N-bit comparator leverages advanced logic technologies to achieve enhanced speed, reduced power consumption, and improved reliability. The design incorporates a combination of parallel comparison architecture and optimized logic gates to ensure efficient operation for multi-bit inputs.
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Design and Implementation of Comparator circuit using Advanced Logic Technologies.pdf
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References
- 1. Tang, X., Shen, L., Kasap, B., Yang, X., Shi, W., Mukherjee, A., ... & Sun, N. (2020). An energy-efficient comparator with dynamic floating inverter amplifier. IEEE Journal of Solid-State Circuits, 55(4), 1011-1022.
- 2. Chua, C., Kumar, R. B. N., & Sireesha, B. (2017). Design and analysis of low-power and area efficient N-bit parallel binary comparator. Analog Integrated Circuits and Signal Processing, 92(2), 225-231.
- 3. Tyagi, P., & Pandey, R. (2020). High‐speed and area‐efficient scalable N‐bit digital comparator. IET Circuits, Devices & Systems, 14(4), 450-458.
- 4. "Rajora, R., Sharma, K., & Sharma, A. (2023, April). 1-Bit Comparator Designed by Multithreshold FinFET based Sleep Transistor Technique in 18nm. In 2023 International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE) (pp. 1-5). IEEE.
- 5. Zahoor, F., Hussin, F. A., Khanday, F. A., Ahmad, M. R., Nawi, I. M., & Gupta, S. (2021, July). Carbon nanotube field effect transistor and resistive random access memory based 2-bit ternary comparator. In 2020 8th International Conference on Intelligent and Advanced Systems (ICIAS) (pp. 1-6). IEEE.
- 6. "Karunakaran, S., Pavan, K., & Reddy, P. R. (2021, December). VLSI Implementation of a High Speed and Area efficient N-bit Digital CMOS Comparator. In 2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE) (pp. 1-4). IEEE.