FPGA for Exascale: Flexibility in the execution model and high-level dataflow abstractions for programmability

The increasing performance demands and the associated energy costs in HPC call for energy efficient architectures able to satisfy this need. FPGAs are an ideal candidate thanks to their reconfigurability, but present limitations in the flexibility of their execution model and their programmability. The work presented here addresses both issues, first, by leveraging dynamic partial reconfiguration for preemptive execution and, second, by providing and demonstrating a methodology for enabling high-level languages other than C/C++ in HLS and by bridging the programmability gap through dataflow abstractions in MLIR.