The NEORV32 RISC-V Processor

What's Changed

• [rtl] add generic cache module (not used yet) by @stnolting in https://github.com/stnolting/neorv32/pull/842
• rtl cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/843
• ⚠️ remove Wishbone tag signal by @stnolting in https://github.com/stnolting/neorv32/pull/845
• ⚠️⚠️ Rename external bus interface by @stnolting in https://github.com/stnolting/neorv32/pull/846
• ✨ Add optional external bus interface cache (XCACHE) by @stnolting in https://github.com/stnolting/neorv32/pull/849
• :warning: processor configuration edits / clean-ups by @stnolting in https://github.com/stnolting/neorv32/pull/850
• Minor cache updates by @stnolting in https://github.com/stnolting/neorv32/pull/851
• [litex] update core complex wrapper by @stnolting in https://github.com/stnolting/neorv32/pull/852
• rework cache system by @stnolting in https://github.com/stnolting/neorv32/pull/853
• Connected SPI bus to on-board Flash and SPI peripheral by @lovelesh-mis in https://github.com/stnolting/neorv32/pull/854
• Update CFU example: use XTEA as "real world" demo application by @stnolting in https://github.com/stnolting/neorv32/pull/855
• Updated Performance test by @mikaelsky in https://github.com/stnolting/neorv32/pull/844

New Contributors

• @lovelesh-mis made their first contribution in https://github.com/stnolting/neorv32/pull/854

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.6...v1.9.7