The NEORV32 RISC-V Processor

What's Changed

• fix trap priority by @stnolting in https://github.com/stnolting/neorv32/pull/784
• Add support for page fault exceptions by @stnolting in https://github.com/stnolting/neorv32/pull/786
• [cpu] fix minor bug in instruction request bus by @stnolting in https://github.com/stnolting/neorv32/pull/790
• Fix for issue #785: FPU fflags no being asserted correctly by @mikaelsky in https://github.com/stnolting/neorv32/pull/788
• 🐛 [cpu] fix non-stable privilege signal of instruction interface by @stnolting in https://github.com/stnolting/neorv32/pull/792
• [CPU] close further illegal instruction loopholes by @stnolting in https://github.com/stnolting/neorv32/pull/797
• ✨ add optional XIP cache by @stnolting in https://github.com/stnolting/neorv32/pull/799
• add fence signal to CPU bus by @stnolting in https://github.com/stnolting/neorv32/pull/800
• :bug: fix fence signal pass-through in caches by @stnolting in https://github.com/stnolting/neorv32/pull/802
• [rtl] fix HPM null range assertions by @stnolting in https://github.com/stnolting/neorv32/pull/803
• minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/804
• Fixes to the FPU for issue #791 by @mikaelsky in https://github.com/stnolting/neorv32/pull/794
• :bug: fix another C-ISA loophole by @stnolting in https://github.com/stnolting/neorv32/pull/806
• Add DMA fence operation by @stnolting in https://github.com/stnolting/neorv32/pull/807

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.4...v1.9.5