The NEORV32 RISC-V Processor

What's Changed

• [rtl] minor cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/764
• [rtl] optimize bus switch by @stnolting in https://github.com/stnolting/neorv32/pull/769
• :bug: Remove RVC float load/store instructions by @stnolting in https://github.com/stnolting/neorv32/pull/771
• ✨ add optional CPU clock gating by @stnolting in https://github.com/stnolting/neorv32/pull/775
• :bug: fix typo that renders the clock gating useless by @stnolting in https://github.com/stnolting/neorv32/pull/776
• [rtl] improve CPU front end by @stnolting in https://github.com/stnolting/neorv32/pull/777
• Updated FIFO NULL assertion fix by @mikaelsky in https://github.com/stnolting/neorv32/pull/778
• set top entiy input defaults to 'L' or 'H' by @stnolting in https://github.com/stnolting/neorv32/pull/779
• 🧪 extend switchable clock domain by @stnolting in https://github.com/stnolting/neorv32/pull/780
• Fix for issue #782 by @mikaelsky in https://github.com/stnolting/neorv32/pull/783

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.3...v1.9.4