Research Artifact for FPGA '24: Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing

Welcome! This is the research artifact of our manuscript: Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing, which will be presented at the 32nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '24).

The artifact is organized as follows:

• Location for the experiments: dhls-formal/fpga24_experiments/
• Location for the modified version of Dynamatic: dhls-formal/etc/dynamatic
• Location for the Python library used for our experiments: dhls-formal/dave/dave/
• The LP model for latency balancing: dhls-formal/dave/dave/latency_balancing
• The LP model for occupancy balancing: dhls-formal/dave/dave/buffer_sizing

The instructions for running the experiments are located in dhls-formal/fpga24_experiments/README.md

Note for artifact reviewer: please contact us (jxu@ethz.ch) for access to the VirtualBox VM file that has all the environments pre-configured.