The NEORV32 RISC-V Processor

What's Changed

• Fix comment mistake by @Unike267 in https://github.com/stnolting/neorv32/pull/727
• [SPI] re-add high-speed mode by @stnolting in https://github.com/stnolting/neorv32/pull/730
• [XIP] add clock divider for fine-tuning by @stnolting in https://github.com/stnolting/neorv32/pull/731
• 🐛 [FPU] fix wiring of exception flags by @stnolting in https://github.com/stnolting/neorv32/pull/733
• 🐛 fix bug in instruction-misaligned exception handling by @stnolting in https://github.com/stnolting/neorv32/pull/734
• [rtl] cleanup & rework/optimize CPU branch system by @stnolting in https://github.com/stnolting/neorv32/pull/735
• ✨ Add "ASIC style" register file option by @stnolting in https://github.com/stnolting/neorv32/pull/736
• [rtl] Cleanup/update assertions and "auto-configuration" by @stnolting in https://github.com/stnolting/neorv32/pull/738
• Update hardware tigger module (Sdtrig) to version 1.0 by @stnolting in https://github.com/stnolting/neorv32/pull/739
• Add menvcfg[h] CSRs by @stnolting in https://github.com/stnolting/neorv32/pull/741
• [RTE] minor updates by @stnolting in https://github.com/stnolting/neorv32/pull/742

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.9.1...v1.9.2