Repository for AutoChip: Automating HDL Generation Using LLM Feedback

AutoChip is designed to generate functional Verilog modules from an initial design prompt and testbench using a selected large language model. Errors from compilation and simulation are fed back into the LLM for repair.

File structure as follows:
 - autochip_scripts: The python scripts which implement the AutoChip framework
 - hdlbits_prompts: The design prompts from HDLBits
 - hdlbits_testbenches: Verilog testbenches for the HDLBits problems
 - README: Setup and usage instructions
 - LICENSE: Apache 2.0 license file