Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Scenario-aware-Data-Flow Graphs (SADFGs), first intro-
duced in [5], achieve a good trade-off between expressiveness
(allowing the expression of more dynamic behaviors than
Synchronous Data-Flow [2] graphs (SDFGs)) and analyzabil-
ity. Finite-State-Machine Scenario-Aware-Data-Flow (FSM-
SADF) [4] graphs are a further simplification of the general
SADF graphs. Both extend SDFGs with scenarios. In an FSM-
SADF MoC a set of typical scenarios are pre-defined (through
a finite state machine) for a specific SDF application. The
SDF application reacts to every scenario in a different manner
leading to more efficiency and better throughput.

In this work, we extend our previous model-checking based
real-time analysis approach in [1] for the analysis of timing
bounds for FSM-SADFGs mapped on a shared memory multi-
core architecture (1a).