Published July 1, 2017 | Version v1
Journal article Restricted

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Authors/Creators

  • 1. OFFIS e.V., Germany
  • 2. University of Siegen, Germany
  • 3. IK4-Ikerlan Technology Research Centre, Spain
  • 4. FentISS, Spain
  • 5. Imperas, United Kingdom
  • 6. CAF Signalling, Spain
  • 7. KTH Royal Institute of Technology, Sweden
  • 8. Saab, Sweden

Description

With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

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