FMPS on MIC

The Finite Element Method software system FMPS is briefly introduced and an overview is given of
development work done by HLRS and VSB concerning the acceleration of solutions to problems yielded by
FMPS using Intel’s Many Integrated Core architecture.
HLRS implemented a hybrid MPI/OpenMP Conjugate Gradient solver. A different scaling behaviour when
using Intel Xeon Phi cards due to a different message transportation (involving a PCIe 2.0 bus) is revealed.
VSB shows that the number of iterations of a Conjugate Gradient solver can be significantly reduced by using a
Deflated Conjugate Gradient scheme, involving the need for an additional solution to a dense linear system by a
LU factorisation. The solution to the dense system can be accelerated using MIC cards.