Published July 26, 2023
| Version v1.8.7
Software
Open
The NEORV32 RISC-V Processor
Authors/Creators
Description
What's Changed
- demo_blink_led_asm bugfix by @vivi202 in https://github.com/stnolting/neorv32/pull/639
- Minor rtl edits, cleanups and optimizations by @stnolting in https://github.com/stnolting/neorv32/pull/641
- Minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/646
- ⚠️ Rework SoC bus system and memory map by @stnolting in https://github.com/stnolting/neorv32/pull/648
- ⚠️ Remove UART sim-mode's 32-bit dump by @stnolting in https://github.com/stnolting/neorv32/pull/650
- ✨ Add support for RISC-V A ISA extension (atomic memory access) by @stnolting in https://github.com/stnolting/neorv32/pull/651
- Minor rtl edits by @stnolting in https://github.com/stnolting/neorv32/pull/652
- [rtl] Optimize bus system and customization options by @stnolting in https://github.com/stnolting/neorv32/pull/653
- :bug: fixing some LR/SC design flaws by @stnolting in https://github.com/stnolting/neorv32/pull/654
- @vivi202 made their first contribution in https://github.com/stnolting/neorv32/pull/639
Full Changelog: https://github.com/stnolting/neorv32/compare/v1.8.6...v1.8.7
Notes
If you use this project, please cite it as below.
Files
stnolting/neorv32-v1.8.7.zip
Files
(6.2 MB)
| Name | Size | Download all |
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md5:9e0083003fdd2c208ae57dc34b693848
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6.2 MB | Preview Download |
Additional details
Related works
- Is supplement to
- https://github.com/stnolting/neorv32/tree/v1.8.7 (URL)