CTD2022: Linearized Track-Fitting on an FPGA

For the ATLAS experiment at the High-Luminosity LHC, a hardware-based track-trigger was originally envisioned, which performs pattern recognition via AM ASICs and track fitting on an FPGA. A linearized track fitting algorithm is implemented in the Track-Fitter that receives track candidates as well as corresponding fit-constants from a database and performs the $\chi^2$-test of the track as well as calculates the helix-parameters. A prototype of the Track-Fitter has been set-up on a Intel Stratix 10 FPGA. Its firmware was tested in simulation-studies and verified on the hardware. The performance of the Track-Fitter has been evaluated in extensive > simulation studies and these results will be presented in this talk.