A Novel Ultra Low-Voltage / Low-Power Rail-to-Rail Comparator Topology in Nanoscale CMOS Technology

The article addresses a novel topology of analog voltage comparator capable of processing the input voltage in rail-to-rail range. We propose two different innovative comparator topologies. One topology is employing a standard “gate-driven” (GD) control of MOS transistors and designed in 65 nm CMOS technology. The other one, designed in 130 nm CMOS technology, uses rather unconventional “bulk-driven” (BD) control of active devices in the circuit. Each  presented circuit topology has its own pros and cons, however both are suitable and actually aimed for ultra low-voltage (ULV) and/or ultra low-power (ULP) applications. The proposed comparator designs have been extensively analyzed for robustness and parameter stability across all fabrication process corners, a wide temperature range (from -20 ◦ C to 85 ◦ C), and for random process variations, as well. Both presented comparator designs can reliably operate
with power consumption in nano-watt range without any fuse trimming or calibration, as the proof of concept has been confirmed by measurements performed on prototype chips.