Published October 22, 2022
| Version 2.0
Dataset
Open
Koios benchmarks' netlist files (BLIF format)
Authors/Creators
- 1. University of Texas at Austin
- 2. University of Toronto
- 3. University of New Brunswick
Description
Koios is a benchmark suite for FPGA architecture and CAD exploration. It contains circuits from the Deep Learning domain.
Here we are uploading the netlist files for these designs obtained by synthesizing the Verilog designs using Intel Quartus for Intel Stratix IV architecture.
For more details see:
https://docs.verilogtorouting.org/en/latest/vtr/benchmarks/#koios-benchmarks
https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow/benchmarks/verilog/koios
Files
Files
(201.6 MB)
| Name | Size | Download all |
|---|---|---|
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md5:cbc049963e18c8fdd52b26d549ff3595
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201.6 MB | Download |
Additional details
Funding
- U.S. National Science Foundation
- SHF: Medium: Collaborative Research: Predictive Modeling for Next-generation Heterogeneous System Design 1763848