HDC8192: A General Purpose Mixed-Signal CMOS Architecture for Massively Parallel Hyperdimensional Computing

This paper addresses a mixed-mode CMOS circuit
for Hyperdimensional Computing (HDC). HDC is based on the
use of binary vectors with thousands dimensions to represent
data in a holistic way. During the last years HDC has shown
to be a powerful approach to solve classification problems. The
proposed circuit architecture in this paper is made up of an array
of 128 64 (8192) processing units (PUs) with a 1-bit ALU, local
memory and connectivity to their 4 nearest neighbors to run the
basic operations of HDC, i.e, binding, bundling and permutation.
The architecture also includes a module to calculate Hamming
distance to address classification. Post-layout simulations of the
complete system working on various basic operations in 0.18 um
CMOS technology are shown.