Design and Analysis of Hybrid full adder Topology using Regular and Triplet Logic Design

In the recent era, voltage reduction procedure is gaining most attention for achieving minimum energy consumption. Full adder is the primary computational arithmetic block in numerous of the computing executions and hence is the critical component of ALU. Various existing full adders proposed in literature fail to accomplish low power delay product (PDP) and lacks driving strength when used in chains structure. In this paper two new hybrid full adders have been proposed with an aim to achieve low PDP. Further the paper proposes ripple carry adder (RCA) in chain structure using triplet design approach to improve the driving strength. Five different hybrid full adders topologies have been implemented to build 4-bit RCA adder in regular and triplet logic design and PDP improvement is obtained in triplet design approach. All the simulations are done on 45nm technology and performance analysis done over the voltage range 0.6 V to 1.2V in Cadence Virtuoso simulation software. Simulation results are obtained to show that delay and PDP has improved in triplet designing and the proposed hybrid adders represents least PDP among other implemented reference circuits.