Published October 18, 2021 | Version v1
Software Open

rtl2uspec

Authors/Creators

  • 1. Stanford University
  • 2. Arm Research

Description

The rtl2uspec tool proposed in the paper: Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations. 

Files

rtl2uspec.zip

Files (66.8 kB)

Name Size
md5:0844f4c339e3912777c6cfad0816de57
66.8 kB Preview Download

Additional details

Related works

Is cited by
10.1145/3466752.3480087 (DOI)