MPSoC FPGA-BASED RADAR WARNING RECEIVER AND DEINTERLEAVING PULSE ON PULSE ALGORITHMS

Identification of radar pulse signals is a crucial component in a radar warning receiver (RWR). Radar emitters transmit short radio frequency (RF) bursts, known as pulse trains, at specific operating parameters. Radar pulse train information is often stored in a list, known as a pulse descriptor word (PDW), and can be used to identify specific radar emitters. An RWR's primary function is to identify unknown radar signals and produce a PDW used to classify and sort signals for further processing, display, and countermeasures. Extracting RF radar pulse information in a dense and noisy environment without prior knowledge of the signal is challenging in a high-risk real-time scenario. Furthermore, simultaneously received signals and overlapping pulses, known as pulse on pulse, can create complications in identification by creating interference between the signals, leading to loss, hidden, or false information.

To solve the problem of separating multiple received radar pulse trains, known as deinterleaving, and to address pulse on pulse situations, a power envelope-based and a parallel fast Fourier transform-based algorithm was developed to be incorporated with an RWR system. This thesis presents a multi-processor system-on-chip field-programable gate array (MPSoC FPGA)- based hardware implementation of an RWR system including deinterleaving pulse on pulse algorithms and details the implementation environment, including hardware acceleration performance analysis and algorithm results.