RTL Verification and FPGA Implementation of 4x4 Vedic Multiplier

The objective of this paper is to study 4x4 Vedic multiplier.
Multiplication is an important fundamental function in arithmetic operations.
Vedic multiplier using Urdhva-Tiryagbyam sutra is predominant in
performance evaluation of parameters such as power, area & delay. This paper
presents design, verification and FPGA implementation of Vedic multiplier.
Verification is carried out in Questa Sim 10.4e using System Verilog HVL and
design is carried out in Xilinx ISE Design Suite 14.7 using Verilog HDL
environment.