Published September 18, 2013 | Version v1
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Design and Performance Analysis of Various Adders using Verilog

Description

Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Adder (CByA) are discussed and the performance parameters of adders such as area and delay are determined and compared. Various adders are designed using Verilog HDL. Then, they are simulated and synthesized using Xilinx ISE 13.2 for Virtex-6 family device with speed grade -2.

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References

  • [1] Padma Devi, Ashima Girdher, and Balwinder Singh, Improved Carry Select Adder with Reduced Area and Low Power Consumption, International Journal of Computer Applications, vol.3, no.4, pp.14-18,June 2010.
  • [2] R.Uma, Vidya Vijayan, M.Mohanapriya, and Sharon Paul, Area, Delay and Power Comparison of Adder Topologies, International Journal of VLSI Design & Communication Systems, vol.3, no.1, pp.153-168,Feb 2012.
  • [3] Raminder Preet Pal Singh, Praveen Kumar, and Balwinder Singh, Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry Look Ahead Adder, Letters of International Journal of Recent Trends in Engineering, vol.2, no.6, pp. 83-89,Nov 2009.
  • [4] Sarabdeep Singh, Dilip Kumar, Design of Area and Power Efficient Modified Carry Select Adder, International Journal of Computer Applications, vol.33, no.3, pp.14-18,Nov 2011.
  • [5] Xilinx13.4, Synthesis and Simulation Design Guide, UG626 (v13.4) January 19, 2012 (2002); The IEEE website. [Online]. Available: http://www.ieee.org/
  • [6] Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, and Kaushik Roy, Low-Power Digital Signal Processing using Approximate Adders, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp.124-137,Jan 2013.
  • [7] Shivani Parmar, Kirat Pal Singh, Design of High Speed Hybrid Carry Select Adder, Proceedings of IEEE International Conference on Advance Computing, Nanjing, China, pp.1656-1663, 2012.
  • [8] M.A. Raheem, Harsha Gupta, Dr.Kaleem Fatima, Osman Adil, A High Speed Reversible Low-Power Error Tolerant Adder, Asia Pacific Conference on Post Graduate Research in Microelectronics & Electronics, Hyderabad, India, pp.178-183, Dec 2012.
  • [9] Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra, Design of Low Power and High Speed Ripple Carry Adder using Modified Feed through Logic, Proceedings of IEEE International Conference on Communications, Devices and Intelligent Systems, West Bengal, pp.377-380, June 2012.
  • [10] H. Parandeh-Afshar, S.M.Fakhraie, and O.Fatemi, Parallel Merged Multiplier-Accumulator Coprocessor Optimized for Digital Filters, Elsevier Journal of Computers and Electrical Engineering, no.36, pp.864-873, June 2008.