Published October 20, 2015 | Version v1
Journal article Open

RISC Processor Design in VLSI Technology Using the Pipeline Technique

Authors/Creators

Description

This paper presents the design and implementation of a pipelined 9-bit RISC Processor. The various blocks
include the Fetch, Decode, Execute and Store result to implement 4 stage pipelining. Harvard Architecture is used
which has distinct program memory space and data memory space. The only load and store is used to communicate
with data memory. RISC using pipeline makes CPI as 1 and improves speed of execution. Verilog Language is used for
coding purpose. The proposed architecture is then simulated using Modelsim.

Files

RISC_Processor_Design_in_VLSI_Technology_Using_the_Pipeline_Technique.pdf

Files (646.0 kB)

Additional details

References

  • [1] R. Uma, Mar-Apr 2012, “Design and Performance Analysis of 8-bit RISC Processor using Xilinx Tool”
  • [2] Galani Tina G., Riya Saini and R.D.Daruwala, July-2013, “Design and Implementation of 32 – bit RISC Processor using Xilinx”
  • [3] Galani Tina R.D.Daruwala, February 2013, “ Performance Improvement of MIPS Architecture by Adding New Features”
  • [4] Samiappa Sakthikumaran,S.Salivahanan and V.S.Kaanchana Bhaaskaran , June 2011, “16-Bit RISC Processor Design For Convolution Application”,IEEE International Conference on Recent Trends In Information Technology, pp.394-397.
  • [5] Rohit Sharma, Vivek Kumar Sehgal, Nitin Nitin1, Pranav Bhasker, Ishita Verma , 2009, “Design And Implementation Of 64-Bit RISC Processor Using VHDL”,UKSim : 11th International Conference on Computer Modeling And Simulation, pp. 568 – 573.
  • [6] Rupali S. Balpande and Rashmi S. Keote.2011, “Design of FPGA based Instruction Fetch & Decode Module of 32-bit RISC (MIPS) Processor, International Conference on Communication Systems and Network Technologies pp. 409 – 413
  • [7] Xiao Li, Longwei Ji, Bo Shen, Wenhong Li, Qianling Zhang, “VLSI implementation of a High-performance 32-bit RISC Microprocessor”, Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on ,Volume 2, 2002 ,pp.1458 – 1461.
  • [8] Kusumlata Pisda, Deependra Pandey, “Realization & Study of High Performance MIPS RISC Processor Design Using VHDL”, International Journal of Emerging trends in Engineering and Development, Volume 7, Issue 2, November 2012, pp. 134 – 139, ISSN: 2249 – 6149.
  • [9] Kirat Pal Singh, Shivani Parmar, “VHDL Implementation of a MIPS – 32 bit Pipeline Processor”, International Journal of Applied Engineering Research, Volume 7, Issue 11, ISSN: 0973 – 4562.