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Published January 25, 2019 | Version v1
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An Improved Fault Tolerant Technique of Median Filter

Authors/Creators

  • 1. PG scholar, Department of Electronics & Communication Engineering, APJ Abdul Kalam Technological University, Trivandrum, Kerala, India
  • 2. Professor, Department of Electronics & Communication Engineering, APJ Abdul Kalam Technological University, Trivandrum, Kerala, India

Description

Acquisition noises in the digital image processing system basically made out of imprudent
clamors, for example, hot and dead pixels, and for the most part expelled utilizing middle
channels. The median filtering algorithm can be speedup by FPGA implementation.
Configuration memory cells in SRAM based FPGAs are susceptible to radiation effects such
as SEUs which leads to configuration memory bit flips and hence a protective measure is
required for the proper operation of median filtering algorithm.The fault tolerant
implementations of median filter provides a range for median value with which the calculated
median value is checked and find out error if the median is out of the provided range. The
main aim of the project is to fasten up the fault tolerant implementation of median filter in
FPGAs by adding a few resources. Experimental results show that the proposed technique
significantly reduces the latency of the fault tolerant median filtering process.

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Additional details

References

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Subjects

Computer Science / IT Journals
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