Published December 31, 2016 | Version v1

DIRECTORY BASED CACHE COHERENCY, ORGANIZATION, OPERATIONS AND CHALLENGES IN IMPLEMENTATION - STUDY

  • 1. Department Computer Application, Srinivas Institute of Management Studies, Mangalore, Karnataka
  • 2. Professor, Department of Computer Science, Srinivas Institute of Technology, Mangalore, Karnataka

Description

Todays systems are designed with Multi Core Architecture. The idea behind this is to achieve high system throuput. Once the Processor clock speed reached its saturation, designers opted for having multiple cores. Each Core or Processor equipped with their own private cache memory. But under Chip Multiprocessor, where all the processor have access to shared memory, having respective cache memory will result with Cache Coherency Problem.   In Directory Protocol, for each block of data there is a directory entry that contains a number of pointers. The purpose of this number is to mention the locations of block copies. The important advantage of directory based protocols is that they scale much better than snoopy protocols. In addition to this it has the advantage of ability to exploit arbitrary point-to-point interconnects. But mean time it also has the overhead in terms of the storage and manipulation of directory state. This paper discus different Directory Based implementation, operations along with and its implementation difficulties.

Files

8.pdf

Files (43.0 kB)

Name Size Download all
md5:189513d8d7c48ca9345146240d6f77de
43.0 kB Preview Download

Additional details

References

  • 1. Design and Implementation of a Directory based Cache Coherence Protocol by Dimitris Tsaliagos Technical Report FORTH-ICS/TR-418 May 2011 2. Effects of cache coherency in Multiprocessors, By Michel Dubois, Member- IEEE, and Faye A. Briggs, Member-IEEE 3. Prof. M. Shaaban's EECC 756 Lecture notes on Cache Coherence Problem in Shared Memory Multiprocessor. 4. Parallel Computer Architecture (PCA) BY David E. Culler and Jaswinder P. Singh (1999 edition). 5. http://parasol.tamu.edu/~rwerger/Courses/654/cachecoherence1.pdf 6. CS252 Graduate Computer Architecture. A course by David A. Patterson in CS Department of UC Berkeley. 7. Cache Coherence Directories for Scalable Multiprocessors -Rrichard Simoni-Stanford, California - Technical report 8. Subrahmanya Bhat & K. R. Kamath, Directory Organizations in Cache Coherency Systems for High Performance Computation, International Journal of Current Research and Modern Education (IJCRME), Volume I, Issue I, p.p 868-871, (August,2016), ISSN (Online): 2455 – 5428 9. Subrahmanya Bhat & Dr. K. R. Kamath, Directory Based Cache Coherency Protocol In Multi-Core System For High Performance Computation, International Journal of Current Research and Modern Education (IJCRME) Volume I, Issue I, pp. 257-261, (May 2016), ISSN : 2455 – 5428 10. Subrahmanya Bhat B and Dr. K.R Kamath, Cache Hierarchy in Modern Processors and Its Impact on Computing, International Journal of Management, IT and Engineering (IJMIE), Volume 5, Issue 7, pp. 248-253, (July 2015), ISSN: 2249-0558, I.F. 5. 299 11. Subrahmanya Bhat & K. R. Kamath, Optimization Approaches in Directory based Cache Coherency Systems for High Performance Computation, International Journal of Current Research and Modern Education (IJCRME), ----Volume I, Issue I, p.p 868-871, (August,2016), ISSN (Online): 2455 – 5428